TI Optimizations: Allocating TI-Cached Memory Pool. ![]() ![]() unavailable.īased upon Swansea University Computer Society NET3.039 Page-cache hash table entries: 4096 (order: 2, 16384 bytes)Ĭhecking for 'wait' instruction. Mount-cache hash table entries: 512 (order: 0, 4096 bytes)īuffer-cache hash table entries: 1024 (order: 0, 4096 bytes) Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) 149.91 BogoMIPSįreeing Adam2 reserved memory Primary data cache 16kb, linesize 16 bytes (4 ways) Primary instruction cache 16kb, linesize 16 bytes (4 ways) All Rights Reserved.Ĭopyright (C) 2003 Texas Instruments Incorporated Copyright (C) 1999-2003 Igor Pavlov. ![]() (c) Copyright 2002-2004 Texas Instruments, Inc. Last reset cause: Software reset (memory controller also reset)
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